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Search - fft in vhdl

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[Algorithm] fft_32K

Description: 32K点的fftVHDL实现,可直接在可编程逻辑器件上运行实现-32K fftVHDL points, which could be directly in the programmable logic device to achieve run
Platform: | Size: 1121280 | Author: kouwei | Hits:

[VHDL-FPGA-Verilog] DMADMA_fanli

Description: 详细介绍nios DMA范例,很有帮助的.-Nios DMA detailed examples, very helpful.
Platform: | Size: 6144 | Author: 朱蒙蒙 | Hits:

[Other] datang(FPGA)

Description: 大唐电信FPGA设计经验.pdf 对初涉及FPGA者来说，无疑是很好的指导。 从开始就让别人的经验成为自己的习惯-Datang Telecom FPGA design experience. Pdf for the beginning of persons involved in FPGA is undoubtedly in good hands. From the beginning the experience of others and become their own habits
Platform: | Size: 967680 | Author: 高 | Hits:

[Algorithm] xfft16_beh_vhdl

Description: 能实现16位的快速傅立叶变化,位数可自由设定,输出斜波可调整个数-Can realize the fast Fourier 16 changes in the median can be free to set up, the output ramp adjustable number of
Platform: | Size: 152576 | Author: 胡召宇 | Hits:

[VHDL-FPGA-Verilog] FFT8

Description: 本设计根据OFDM系统的实际需要，提出一种用FPGA实现FFT运算的方案，并以64点FFT为例，在Quartus II软件上通过了综合和仿真。-The design of OFDM systems in accordance with the actual needs of a computing using FPGA realize FFT program, and 64-point FFT as an example, in the Quartus II software through a comprehensive and simulation.
Platform: | Size: 27648 | Author: 叶开 | Hits:

[Algorithm] CORDIC

Description: cordic算法，包含所有的CORDIC的算法，与发表过的论文，与实现方案-CORDIC algorithm, contains all of the CORDIC algorithm, and published papers, and implementation of programs
Platform: | Size: 8102912 | Author: elisen | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: Verilog教程，讲述Verilog在cpld/fpga中从设计到仿真全过程。-Verilog tutorial, Verilog described in cpld/fpga simulation from the design to the entire process.
Platform: | Size: 2479104 | Author: pangyugang | Hits:

[VHDL-FPGA-Verilog] fft16ref

Description: VHDL fft 源程序，直接运行就可以，很好的一个程序-VHDL fft source code can be run directly, a very good program
Platform: | Size: 1123328 | Author: 苗哥 | Hits:

[VHDL-FPGA-Verilog] fftipcore

Description: 实现fft的ip核，用vhdl语言实现。-Fft realize the ip nuclear, using VHDL language.
Platform: | Size: 31744 | Author: liu | Hits:

[Other] VHDL_Core_for_1024_Point_Radix_4_FFT_Computation.

Description: This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx庐 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
Platform: | Size: 456704 | Author: alex | Hits:

[VHDL-FPGA-Verilog] fft

Description: 基于FPGA的FFT的硬件实现。其中含有部分vhdl程序，本论文采用基4FFT算法-FPGA-based hardware implementation of the FFT. Vhdl part which contains the procedures used in this paper-based algorithm 4FFT
Platform: | Size: 942080 | Author: xyyj | Hits:

[VHDL-FPGA-Verilog] CORDIC

Description: 数字控制振荡器（NCO，numerical controlled oscillator）是软件无线电、直接数据频 率合成器（DDS，Direct digital synthesizer）、快速傅立叶变换（FFT，Fast Fourier Transform） 等的重要组成部分，同时也是决定其性能的主要因素之一，随着芯片集成度的提高、在信号 处理、数字通信领域、调制解调、变频调速、制导控制、电力电子等方面得到越来越广泛的 应用。-Digital controlled oscillator (NCO, numerical controlled oscillator) is a software-defined radio, direct data on the frequency synthesizer (DDS, Direct digital synthesizer), Fast Fourier Transform (FFT, Fast Fourier Transform), such as an important component of the decision at the same time the performance of one of the main factors, along with the improvement of the chip integrated in the signal processing, digital communications, modulation and demodulation, frequency conversion speed control, guidance control, such as power electronics get more and more widely.
Platform: | Size: 4096 | Author: 司令 | Hits:

[VHDL-FPGA-Verilog] Quartus_fft_ip_core

Description: Quartus中fft ip core的使用(modelsim 仿真FFT ip core 结合QUARTUS II 联合调试)-Fft ip core in Quartus use (modelsim simulation FFT ip core integration QUARTUS II Joint Commissioning)
Platform: | Size: 299008 | Author: 刘晓彬 | Hits:

[Mathimatics-Numerical algorithms] dft

Description: verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!
Platform: | Size: 1024 | Author: 刘庆 | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[Embeded-SCM Develop] butterfly

Description: 　计算离散傅里叶变换的一种快速算法,简称FFT。快速傅里叶变换是1965年由J.W.库利和T.W.图基提出的。采用这种算法能使计算机计算离散傅里叶变换所需要的乘法次数大为减少,特别是被变换的抽样点数N越多,FFT算法计算量的节省就越显著。 -Discrete Fourier transform calculation of a fast algorithm, referred to as FFT. Fast Fourier Transform in 1965 by JW Cooley and TW map out Kormakiti. This algorithm enables calculation of discrete Fourier transform computer required a significant reduction in the number of multiplication, in particular by changing the sampling points N more, FFT algorithm for calculating the amount of savings will be significant.
Platform: | Size: 1024 | Author: 圈石 | Hits:

[VHDL-FPGA-Verilog] fft_gen

Description: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
Platform: | Size: 6144 | Author: Jayesh | Hits:

[VHDL-FPGA-Verilog] cf_fft

Description: FFT using C and VHDL. can compute upto 1K, 2K and 4K in radix 2.
Platform: | Size: 3318784 | Author: mimi | Hits:

[VHDL-FPGA-Verilog] cFFT

Description: CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the CFFT core to be different from the standard FFT algorithm. This variation in gain is not important for orthogonal frequency division modulation (OFDM) and demodulation. The gain can be corrected, to that of a conventional FFT, by applying a constant multiplying factor.
Platform: | Size: 183296 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] 2345676588FPGAxiebofenxi

Description: 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using the FFT for fast FPGA computing, digital phase-locked loop to synchronize the measured signal to reduce the non-synchronous sampling error arising from implementation of the design and implementation are given. Digital PLL and FFT algorithm design and implementation using VHDL language, the program can improve the accuracy of harmonic analysis and response speed, and greatly streamline the hardware circuit, the system is very easy to upgrade.
Platform: | Size: 18432 | Author: 何正亚 | Hits:
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